If the Project Folder parameter is empty, HDL Coder saves the generated files in the current directory. To specify a top-level project folder for the ipcore folder to be stored along with all other generated files, in the Configuration Parameters dialog box, use the Project Folder parameter in the HDL Code Generation > Target tab. After you generate the custom IP core, the IP core files are in the ipcore folder in your current directory. In the Simulink Toolstrip, in the HDL Code tab, click Generate IP Core. Using the Interface Settings tab to configure interface-related settings, such as the register interface and FPGA data capture properties.Īfter you configure the IP core settings and mappings for your design, you can generate an IP core. Using the Clock Settings tab to configure clock-related settings. Using the General tab to configure top-level settings, such as the name of the IP core and whether to generate an IP core report. The LED output port is mapped to an external interface, LEDs General Purpose, which connects to the LED hardware on the Zynq board. In this example, the input ports Blink_frequency and Blink_direction are mapped to the AXI4-Lite interface, so HDL Coder generates AXI interface accessible registers for them. Ensure the Synthesis Tool is set to Xilinx Vivado.Įnsure that the Reference Design parameter is set to Default system.Ĭonfigure your design to map to the target hardware by mapping the DUT ports to IP core target hardware and setting DUT-level IP core options. In the Support Package Installer, select Xilinx Zynq Platform and follow the instructions to complete the installation. If this option does not appear, select Get more to open the Support Package Installer. Set the Target Platform parameter to Xilinx Zynq ZC702 evaluation kit. Open the HDL Code Generation > Target tab of Configuration Parameters dialog box by clicking the Settings button. To remember the selection, you can pin this option. Make sure that Code for is set to this subsystem. Select the led_counter subsystem which is the device under test (DUT) for this example. In the HDL Code tab, in the Output section, set the drop-down button to IP Core. To generate an IP core from the hdlcoder_led_blinking/led_counter subsystem, prepare your model by using the configuration parameters, configure your design by using the IP Core editor, and generate the IP core by using the HDL Code tab of the Simulink Toolstrip. For more information on different ways to generate an IP core using HDL Coder, see Comparison of IP Core Generation Techniques. You can then integrate the generated IP core with a larger FPGA embedded design in the Xilinx Vivado environment.įor an overview of how to generate an IP core for a specific hardware platform, see Targeting FPGA & SoC Hardware Overview. HDL Coder packages the generated files into a folder you specify. HDL Coder generates HDL code from the Simulink blocks, and also generates HDL code for the AXI interface logic that connects the IP core to the embedded processor. The generated IP core is designed to be connected to an embedded processor on an FPGA device. You can generate a reusable IP core module from a Simulink model using HDL Coder. Open_system( 'hdlcoder_led_blinking') Generate HDL IP Core The output port, Read_Back, can be used to read data back to the processor. The output port of the hardware subsystem, LED, connects to the LED hardware. In the embedded software, this means the ARM processor controls the generated IP core by writing to the AXI interface accessible registers. In Simulink, you can use the Slider Gain or Manual Switch block to adjust the input values of the hardware subsystem. All the blocks outside of the subsystem led_counter are for software implementation. Two input ports, Blink_frequency and Blink_direction, are control ports that determine the LED blink frequency and direction. It models a counter that blinks the LEDs on an FPGA board. In this example, the subsystem led_counter is the hardware subsystem. All the blocks inside this subsystem are implemented on programmable logic, and all the blocks outside this subsystem run on the ARM processor. This atomic subsystem is the boundary of your hardware-software partition. Group all the blocks you want to implement on programmable logic into an atomic subsystem. The first step of the Zynq hardware-software co-design workflow is to decide which parts of your design to implement on the programmable logic, and which parts to run on the ARM processor. Partition Design for Hardware and Software Implementation Hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2020.2\bin\vivado.bat')
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